(1) Field of the Invention
This invention relates to the formation of auxiliary alignment marks in the scribline of an integrated circuit wafer. The alignment marks are formed in the same layer of dielectric in which the contact and via holes are formed and are the same size and shape as the contact holes, which prevents overexposure of the alignment marks.
(2) Description of the Related Art
U.S. Pat. No. 5,496,777 to Moriyama describes a method of arranging alignment marks used in different process steps on scribe lines.
U.S. Pat. No. 5,532,520 to Haraguchi et al. describes alignment marks for the X direction alignment of a chip on a semiconductor wafer. The alignment marks comprise recesses and projections which are smaller than the X directional width of a grain on a metal film or the average particle size. The projections may be formed by an insulating layer formed on the semiconductor substrate.
U.S. Pat. No. 5,270,255 to Wong describes a method of metallization of an integrated circuit wafer which provides good step coverage and maintains a useful alignment mark. At least one contact opening to the semiconductor substrate and at least one lithography alignment cross mark opening structure are formed.
U.S. Pat. No. 5,627,624 to Yim et al. describes an integrated circuit test reticle for alignment mark optimization. A test reticle using alignment mark shapes, sizes, and depths is described.
U.S. Pat. No. 5,705,320 to Hsu et al. describes a method of preserving alignment marks after chemical mechanical polishing using a clear out window in the frame area of the contact via reticle.
U.S. Pat. No. 5,640,053 to Caldwell describes an inverse open frame alignment mark.
U.S. Pat. No. 5,271,798 to Sandhu et al. describes a method of selectively removing material from the alignment region of a wafer. Methods of confining etching materials to the alignment region are described.